Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. SRAM cells may include different numbers of transistors and are often accordingly referred to by the number of transistors, for example, six-transistor (6T) SRAM, eight-transistor (8T) SRAM, and the like. The transistors typically form a data latch for storing a bit. Additional transistors may be added to control the access to the transistors. SRAM cells are typically arranged as an array having rows and columns. Typically, each row of the SRAM cells is connected to a word-line, which determines whether the current SRAM cell is selected or not. Each column of the SRAM cells is connected to a bit-line (or a pair of bit-lines), which is used for storing a bit into the SRAM cell or read from the SRAM cell.
With the scaling of integrated circuits, the power supply voltages of integrated circuits are reduced, along with the power supply voltages of memory circuits. Accordingly, read and write margins of the SRAM cells, which determine how reliably the bits of the SRAM cells can be read from and written into, respectively, are reduced. The situation is further worsened by the unexpected reduction in the power supply voltages caused by variations. Due to the existence of static noise, the reduced read and write margins may cause errors in the respective read and write operations.
To improve the write margins, the widths of word-line pulses are desirably extended in response to the drop in the power supply voltages, so that the access time to SRAM cells is also extended. In conventional circuits, however, although methods were provided to extend the widths of word-line pulses, the increase in the widths of word-line pulses was linear to the reduction in the power supply voltages. Accordingly, the increase in the widths of word-line pulses may not be able to satisfy the requirement to suit for the reduction in the power supply voltages. This results in the pre-mature starting of sense amplifiers and in turn causes the failure of write operations.